Skip to content
This repository was archived by the owner on Mar 27, 2025. It is now read-only.

Commit f05f844

Browse files
fix typo
1 parent 55dbaad commit f05f844

File tree

2 files changed

+4
-4
lines changed

2 files changed

+4
-4
lines changed

docs/LoongArch-Vol1-EN/basic-integer-instructions/overview-of-basic-integer-instructions/other-miscellaneous-instructions.adoc

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -325,7 +325,7 @@ That is, information such as "`Loongson3A5000 @ 2.5GHz`"
325325
|`1` indicates that the Cache shown by `L1 IU_Present` is the unified Cache
326326

327327
^m|2
328-
^m|L1 D Prwsent
328+
^m|L1 D Present
329329
|`1` indicates there is a first-level data Cache
330330

331331
^m|3
@@ -377,7 +377,7 @@ That is, information such as "`Loongson3A5000 @ 2.5GHz`"
377377
|`1` indicates there is a three-level data Cache
378378

379379
^m|15
380-
^m|L3 F Inclusive
380+
^m|L3 D Private
381381
|`1` indicates that the three-level data Cache is private to each core
382382

383383
^m|16

docs/Loongson-3A5000-usermanual-EN/la464-processor-core/instruction-set-features-implemented-in-3a5000.adoc

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -252,7 +252,7 @@ m|L1 IU Unify
252252
m|1'b0
253253

254254
^m|2
255-
m|L1 D Prwsent
255+
m|L1 D Present
256256
|`1` indicates there is a first-level data Cache
257257
m|1'b1
258258

@@ -317,7 +317,7 @@ m|L3 D Present
317317
m|1'b0
318318

319319
^m|15
320-
m|L3 F Inclusive
320+
m|L3 D Private
321321
|`1` indicates that the three-level data Cache is private to each core
322322
m|1'b0
323323

0 commit comments

Comments
 (0)