Search Results for "formal verification"

G4LTL-ST is a standalone tool and a Java library for automatically generating industrial control software (supporting IEC-61131-3 Structure Text) from LTL or extended logic specifications. See Tutorial.txt inside the package for step-by-step instructions. For technical demails, see CAV'14 paper "G4LTL-ST: Automatic Generation of PLC Programs". The old version (G4LTL; under BSD license) is available under file\arxiv.

Cress (Communication Representation Employing Systematic Specification) allows graphical description of a wide variety of services such as in data communications/telecommunications, but Cress is not limited to this. The approach allows services to be described graphically as (work)flows of activities. Cress diagrams are automatically translated into formal languages for rigorous analysis and verification, and are also automatically translated into implementation languages for deployment and validation. Cress aims to make service design as easy as possible without requiring specialist development knowledge. It simplifies service creation to drawing diagrams, clicking buttons and defining a few tool parameters. ...

The overall aim of the SafeCap project is to develop modelling techniques and tools for improving railway capacity while ensuring that safety standards are maintained. Useful links: Project homepage: http://http://safecap.co.uk/

Syspect is a tool to specify a system using UML2 diagramms and translate them into a CSP-OZ-DC specification for formal verification.

Java library for manipulating BDDs (Binary Decision Diagrams). Binary decision diagrams are widely used in model checking, formal verification, optimizing circuit diagrams, etc.

The CoreASM project focuses on the design of a lean executable ASM (Abstract State Machines) language, in combination with a supporting tool environment for high-level design, experimental validation and formal verification of abstract system models.

Currently, all existing formal tools are designed to serve as formal verifiers, using one implementation or another. JTLV is a new tool aimed to facilitate and provide a unified framework to the development of formal verification algorithms.

This project is a software and a framework implementing a formal specification generation approach. The tool supports the theory on formal modeling, automated composition and formal verification of system specifications.

This project proposes a tool for formal verification of web services composition based on Pi-calculus and the conversion between BPEL and pi-calculus. This tool integrates two kinds of formal verification techniques and can validate automatically.

Currently, all existing formal tools are designed to serve as formal verifiers, using one implementation or another. NO tool is providing a global framework to develop algorithms. Silicis is a new formal framework for designing [verification] algorithms.