Computer Architecture Concepts and Performance
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G09Deviprasad N shettyComputer Architecture Concepts and Performance
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Powered by AIFlynn's taxonomy classifies parallel computing architectures based on data streams and instruction streams processed concurrently into four categories: SISD (Single Instruction stream, Single Data stream), SIMD (Single Instruction stream, Multiple Data streams), MISD (Multiple Instruction streams, Single Data stream), and MIMD (Multiple Instruction streams, Multiple Data streams). These classifications help in understanding the structural design of computer architectures; for instance, SIMD is used in vector processing where a single instruction operates on multiple data points, while MIMD supports multiprocessor systems applying different instructions on different data streams concurrently .
SRAM (Static RAM) and DRAM (Dynamic RAM) differ mainly in their design and applications. SRAM uses flip-flop circuits for each bit and retains data as long as power is supplied, offering faster access times and higher speed, making it suitable for cache memory. DRAM stores bits as charges in capacitors, requires periodic refreshing, and provides larger storage capacity at a lower cost but with slower access times, making it ideal for main memory. These structural differences influence their uses, with SRAM being used where speed and reliability are critical, and DRAM where larger volume storage at lower cost is desired .
The basic operational concepts of a computer revolve around the central processing unit (CPU), memory, and the input/output system. The CPU performs arithmetic and logic operations and controls other operations. The memory stores data and instructions. The interaction between the processor and memory occurs through the use of registers, which serve as temporary storage for data being processed. Each register has a unique identifier and can hold a specific size of data. The connection involves data transfer between CPU registers, such as through the use of control signals and buses that connect CPU, memory and I/O devices. This connection can be explained with a diagram illustrating the processor, its registers, the system buses, and the memory unit .
Big Endian and Little Endian are two methods of storing multibyte data-types in computer memory. Big Endian stores the most significant byte first, at the lowest address, which aligns with how humans typically read numbers. Little Endian stores the least significant byte first, making it easier for systems to incrementally read the bytes in increasing order of significance. The choice between these affects firmware and software design, especially in systems that rely on binary data exchange between computers, as a mismatch can lead to misinterpretation of data .
A CMOS memory cell stores data using a combination of transistors that form a bistable latch circuit. Its primary advantage is its low power consumption because it only draws significant power during switching between states, making it energy-efficient for static operations. Compared to DRAM, which requires periodic refreshing and higher power for capacitive charge retention, CMOS offers faster access times without the need for constant refreshing, which is beneficial in high-speed circuitry like processor cache .
Synchronous buses utilize a common clock signal to coordinate communication between different components connected to the bus. This ensures that data transfers occur at regular intervals, allowing for predictable performance and simplified control. Asynchronous buses, on the other hand, do not rely on shared timing signals, instead using handshaking and request-acknowledge signals to manage data transfers, which can result in less predictable but more flexible timing, accommodating devices of varied speeds. Synchronous buses offer higher throughput due to reduced overhead, while asynchronous buses provide greater versatility for connecting diverse devices .
Pipelining is a technique where multiple instruction phases are overlapped in processing to increase throughput. It divides instruction execution into separate stages, allowing different instructions to be processed at each stage simultaneously. This approach mimics assembly line work, improving instruction throughput at the cost of increased complexity in instruction handling and potential hazards like data dependencies. It implies faster processing but necessitates sophisticated control logic to optimize the instruction flow and handle stalls or branching efficiently .
Addressing modes provide the rules for interpreting or modifying the address field(s) in the instructions before the operand is executed. This functionality is crucial as it determines how the processor should access the data it requires. Common types of addressing modes include immediate, direct, indirect, register, and indexed. Each mode serves different purposes such as simplifying the implementation of loops, pointers, or arrays in programming languages. For example, the direct addressing mode specifies the effective address of the operand directly within the instruction, while indirect addressing uses the address of a pointer to the operand .
Cache memory is a smaller, faster type of volatile memory that stores copies of frequently accessed data from main memory to reduce average time to access data. Direct mapping assigns each block of main memory to a specific location in cache, making it simple but prone to collisions. Associative mapping allows any block to be loaded into any cache line, offering greater flexibility but requiring complex search mechanisms. Set-associative mapping is a compromise, dividing cache into sets and mapping each block to any location within a set, balancing simplicity and efficiency .
Performance measurement is critical in computing because it provides insights into how effectively a computer can execute processes and handle system tasks. Metrics such as instruction throughput, latency, and execution speed are used to quantify system performance. The SPEC rating is a standardized set of benchmarks that assess computing performance using realistic workload tests, presenting a composite numerical value that facilitates comparison between different systems. This benchmarking helps in understanding potential efficiency and optimizations for various software applications, thereby guiding purchasing or upgrading decisions .
