Revision
Unit – 2
Chapter - 2
Memory Hierarchy: Introduction, basics of cache, measuring and improving of
cache performance, cache memory: associative mapping, direct mapping, set-
associative mapping, cache writing and initialization, virtual memory, common
framework for memory hierarchies. Case study of PIV and AMD opteron memory
hierarchies.
Introduction
• The memory unit is an essential component in any digital computer since it is needed for storing programs and
data.
• The memory unit that communicates directly with the CPU is called the main memory. Devices that provide
backup storage are called auxiliary memory.
Basics of cache, measuring and improving of
cache performance
• A special very-high-speed memory called a cache is sometimes used to increase the speed of
processing by making current programs and data available to the CPU at a rapid rate.
• Analysis of a large number of typical programs has shown that the references to memory at any
given interval of time tend to be confined within a few localized areas in memory. This
phenomenon is known as the property of locality of reference.
• The performance of cache memory is frequently measured in terms of a quantity called hit ratio.
• When the CPU refers to memory and finds the word in cache, it is said to produce a hit.
• If the word is not found in cache, it is in main memory and it counts as a miss.
• The ratio of the number of hits divided by the total CPU references to memory (hits plus misses) is
the hit ratio. The
Cache memory: Associative Mapping
Cache memory: Direct mapping
Cache memory: Set-associative mapping
Cache writing and initialization
• Writing into the cache can be done with the help of two mechanisms
• Write through
• Write back
• The cache is initialized when power is applied to the computer or when the main memory is loaded
with a complete set of programs from auxiliary memory. After initialization the cache is considered
to be empty, but in effect it contains some nonvalid data.
Virtual memory, common framework for
memory hierarchies.
Case study of PIV and AMD opteron memory
hierarchies
Intel Pentium IV (PIV):
1. Registers: PIV had a set of general-purpose and specialized registers for rapid data access.
2. Level 1 Cache (L1): The PIV had separate instruction and data caches, each with 8 KB.
3. Level 2 Cache (L2): The PIV included a larger unified L2 cache, which varied in size between 256 KB and 2 MB, depending
on the specific model.
4. Main Memory (RAM): Data not found in the caches was retrieved from RAM, which was typically DDR SDRAM at the
time.
AMD Opteron:
1. Registers: Like the PIV, the AMD Opteron had a set of registers for fast data access.
2. Level 1 Cache (L1): The L1 cache was divided into two parts: a 64 KB instruction cache and a 64 KB data cache.
3. Level 2 Cache (L2): The Opteron featured a unified L2 cache ranging from 512 KB to 2 MB, depending on the specific
model.
4. Main Memory (RAM): Main memory was typically DDR SDRAM or later variants, similar to the PIV.
