UVM-based verification environment for an I2C controller, built as a course project. Includes constrained-random + directed tests, functional coverage, and protocol checks.

• project_benches/ : testbenches / top-level sims
• verification_ip/ : verification components (agents/monitors/scoreboard as applicable)
• docs/ : notes / diagrams (if any)

• Simulator: Questa/ModelSim (tested on: <YOUR VERSION/OS>)

This repo contains a Makefile-driven flow (see project_benches/ history). From the relevant bench directory, try:

make compile
make sim