📘 UNIT – I : IMPORTANT ANSWERS (10 MARKS EACH)

1 (a) Explain about Computer Design and Computer Architecture

(5 Marks)

Computer Architecture

Computer Architecture refers to the logical structure and programmer-visible

features of a computer system. It defines what the system does.

Key points:

* Instruction Set Architecture (ISA)

* Data types and formats

* Addressing modes

* Register set visible to programmers

* Input and Output mechanisms

Example: Difference between 32-bit and 64-bit processors is an architectural

change.

Computer Design (Organization)

Computer Design refers to the internal hardware implementation of the

system. It explains how the architecture is implemented.

Key points:

* Control unit design

* ALU design

* Memory organization

* Bus structure

* Pipelining and hardware techniques

Difference (one line)

* Architecture defines what the computer does

* Design defines how it is built

Conclusion

Computer Architecture and Computer Design together determine the

performance, functionality, and efficiency of a computer system.

1 (b) What are Computer Registers? Explain

(5 Marks)

Definition

Registers are small, high-speed storage units inside the CPU used to store
data, instructions, and addresses temporarily during execution.

Characteristics

* Fastest memory in the system

* Limited in number

* Directly accessed by CPU

Types of Registers

1. Accumulator (AC) – Stores intermediate results

2. Program Counter (PC) – Holds address of next instruction

3. Instruction Register (IR) – Holds current instruction

4. Memory Address Register (MAR) – Holds memory address

5. Memory Data Register (MDR) – Holds data from/to memory

6. Flag Register – Stores status flags (Zero, Carry, etc.)

Conclusion
Registers improve CPU speed and efficiency by reducing memory access
time and supporting instruction execution.

2 (a) Discuss about Shift Micro-operations

(5 Marks)

Definition

Shift micro-operations are operations that move bits of a register left or right.
These operations are used in multiplication, division, and data manipulation.

Types of Shift Micro-operations

1. Logical Shift

* Shifts bits left or right

* Vacated positions are filled with 0

Types:

* Logical Left Shift (LLS)

* Bits shifted left

* Rightmost bit filled with 0

* Used for multiplication by 2

* Logical Right Shift (LRS)

* Bits shifted right

* Leftmost bit filled with 0

* Used for division by 2 (unsigned numbers)

2. Arithmetic Shift

* Used for signed numbers

* Sign bit is preserved

Types:

* Arithmetic Left Shift (ALS)

* Similar to logical left shift

* May cause overflow

* Arithmetic Right Shift (ARS)

* Sign bit is retained

* Used for signed division by 2

3. Circular Shift (Rotate)

* Bits shifted out from one end re-enter from the other end

Types:

* Rotate Left

* Rotate Right

Conclusion

Shift micro-operations are essential for efficient arithmetic operations and

data processing in a CPU.

2 (b) List and Explain Memory-Reference Instructions

(5 Marks)

Definition

Memory-reference instructions are instructions that access memory locations

to perform operations. These instructions use an address field to specify
memory operands.

Types of Memory-Reference Instructions

1. AND

* Performs logical AND between AC and memory content

* Result stored in AC

2. ADD

* Adds memory content to AC

* Result stored in AC

3. LDA (Load Accumulator)

* Loads data from memory into AC

4. STA (Store Accumulator)

* Stores contents of AC into memory

5. BUN (Branch Unconditional)

* Transfers control to specified memory address

6. BSA (Branch and Save Return Address)

* Used for subroutine calls

7. ISZ (Increment and Skip if Zero)

* Increments memory content by 1

* Skips next instruction if result is zero

Conclusion

Memory-reference instructions allow the CPU to perform arithmetic, logic,

and control operations using memory data, making them fundamental to
program execution.

3 (a) Difference between Computer Organization and Computer Architecture

(5 Marks)

Computer Architecture
Computer Architecture refers to the functional and logical aspects of a
computer system that are visible to the programmer. It defines what the
system does.

Key Points:

* Instruction set (ISA)

* Data types and formats

* Addressing modes

* Register set visible to programmer

* Input and output mechanisms

Example: 32-bit vs 64-bit processors.

Computer Organization

Computer Organization refers to the internal hardware structure and

implementation of the computer system. It explains how the system is built.

Key Points:

* Control unit design

* ALU implementation

* Memory organization

* Bus structure

* Hardware interconnections

Differences

Computer Architecture Computer Organization

Programmer visible Hardware oriented

Logical structure Physical implementation

Defines functionality Defines performance

Conclusion
Architecture specifies what the computer should do, while organization
explains how it is implemented internally. Both together ensure efficient
system design.

3 (b) Short Note on Instruction Code Format

(5 Marks)

Definition

Instruction Code Format defines the structure of a machine instruction,

specifying how the instruction is divided into different fields.

Basic Fields of Instruction Code

1. Opcode Field

* Specifies the operation to be performed

* Example: ADD, SUB, LOAD, STORE

1. Address Field

* Specifies the memory location of operand

* Can be one or more addresses

1. Mode Field (Addressing Mode)

* Specifies how the operand is accessed

* Example: immediate, direct, indirect

Types of Instruction Formats

1. Three-Address Instruction

* Contains opcode + 3 address fields

* Faster execution, larger instruction size

1. Two-Address Instruction

* One operand also acts as destination

1. One-Address Instruction

* Uses accumulator implicitly

1. Zero-Address Instruction

* Uses stack for operands

Conclusion

Instruction code format helps the CPU decode instructions efficiently and
determines the instruction length and execution speed.

5. Explain the following.

a) Register transfer b) Input-Output and interrupt 02-02-2024C) Explain in

detail life cycle

of instruction

(a) Register Transfer

Definition

Register Transfer refers to the movement of data from one register to

another within the CPU. It is the basic operation performed during instruction
execution.

Register Transfer Language (RTL)

Register transfers are expressed using RTL notation.

Example:

R2 ← R1

This means the contents of register R1 are transferred to register R2.

Types of Register Transfer Operations

1. Data Transfer – Copying data between registers

2. Arithmetic Operations – ADD, SUB using registers

3. Logical Operations – AND, OR, XOR

4. Shift Operations – Left shift, right shift

Importance

* Enables internal data movement

* Forms the basis of micro-operations

* Improves CPU speed

(b) Input–Output and Interrupt

Input–Output (I/O)

Input–Output refers to the communication between the CPU and external

devices such as keyboard, mouse, printer, and disk.

I/O Techniques:

* Programmed I/O

* Interrupt-driven I/O

* Direct Memory Access (DMA)

Interrupt

An interrupt is a signal sent to the CPU to get immediate attention for an

event.

Interrupt Process:

1. CPU completes current instruction

2. Saves Program Counter (PC)

3. Executes Interrupt Service Routine (ISR)

4. Returns to main program

Advantages

* Avoids continuous polling

* Improves CPU efficiency

* Faster response to I/O devices

(c) Life Cycle of an Instruction (Instruction Cycle)

Definition

The instruction life cycle refers to the sequence of steps followed by the CPU
to execute an instruction.

Stages of Instruction Cycle

1. Fetch Cycle

* Instruction is fetched from memory

* PC is incremented

2. Decode Cycle

* Opcode is decoded

* Type of instruction is identified

3. Execute Cycle

* Required operation is performed

* ALU, registers, or memory are used

4. Interrupt Cycle (if any)

* CPU checks for interrupt

* ISR is executed if interrupt occurs

Conclusion

The instruction life cycle ensures systematic execution of programs, efficient

use of hardware, and proper handling of interrupts.

6. (a) Draw the block diagram of a digital computer and explain the purpose
of each part
(5 Marks)

Block Diagram of a Digital Computer

(A neat block diagram should contain: Input Unit, CPU (ALU + Control Unit +
Registers), Memory Unit, Output Unit)

Main Components and Their Functions

1. Input Unit

* Accepts data and instructions from the user

* Converts them into machine-readable (binary) form

* Examples: Keyboard, Mouse, Scanner

2. Central Processing Unit (CPU)

The CPU is the brain of the computer and performs all processing tasks.

a) Arithmetic Logic Unit (ALU)

* Performs arithmetic operations (addition, subtraction)

* Performs logical operations (AND, OR, NOT)

b) Control Unit (CU)

* Controls and coordinates all operations

* Fetches and decodes instructions

* Generates control signals

c) Registers

* High-speed storage inside CPU

* Store instructions, data, and intermediate results

3. Memory Unit

* Stores programs, data, and results

* Types: Primary memory (RAM, ROM)

4. Output Unit

* Converts processed data into human-readable form

* Examples: Monitor, Printer, Speaker

Conclusion

A digital computer works by accepting input, processing it using the CPU,

storing data in memory, and producing output efficiently.

6. (b) Design a 4-bit combinational circuit decrementer using four full-adder

circuits

(5 Marks)

Definition

A decrementer is a combinational circuit that subtracts 1 from a binary

number.

Concept

To decrement a 4-bit number, we add the 2’s complement of 1, i.e.:

Decrementer = A − 1 = A + (1111)₂

Design Using Full Adders

* Use four full adders

* One input of each full adder is connected to the input bits: A3 A2 A1 A0

* The other input is connected to logic 1

* Carry-in of the least significant full adder = 0

Operation
* FA0 subtracts 1 from A0

* Borrow is propagated through FA1, FA2, FA3

* Output gives A − 1

Conclusion

A 4-bit decrementer can be efficiently designed using four full adders,

making it a simple and fast combinational circuit.

7. (a) Difference between Direct and Indirect Address Instructions

(5 Marks)

Direct Address Instruction

* Address field contains the actual memory address of the operand

* Operand is accessed directly

Memory References Required:

* 1 for instruction fetch

* 1 for operand access

Total = 2 memory references

Indirect Address Instruction

* Address field contains the address of a memory location that stores the
operand address

* Requires an extra memory access

Memory References Required:

* 1 for instruction fetch

* 1 to get effective address

* 1 to get operand
Total = 3 memory references

Comparison Table

Feature DirectIndirect

Operand address Given directly Obtained indirectly

Memory access Faster Slower

Flexibility Less More

Conclusion

Direct addressing is faster, while indirect addressing provides greater

flexibility.

7. (b) Demonstrate construction of a common bus system with multiplexers

(5 Marks)

Definition

A common bus system allows multiple registers to share a single

communication path using multiplexers.

Construction Using Multiplexers

* Each bit of the bus uses one multiplexer

* Inputs of multiplexers are connected to corresponding bits of registers

* Selection lines decide which register places data on the bus

Example

* For 4 registers, each multiplexer is 4×1

* Selection lines S1 and S0 choose the register

* Output of all multiplexers forms the common bus

Advantages

* Reduces hardware complexity

* Avoids multiple point-to-point connections

* Efficient data transfer between registers

Conclusion

A common bus system using multiplexers provides an organized and

economical method for data transfer within a computer system.

UNIT - II

1. (a) What are Shift Instructions? Explain with suitable examples

(5 Marks)

Definition

Shift instructions are used to shift the bits of a register either to the left or
right. They are mainly used in arithmetic operations, data manipulation, and
bit-level processing.

Types of Shift Instructions

1. Logical Shift

* Vacant bit positions are filled with 0

Example:

Logical Left Shift

1010 → 0100

(Multiplication by 2)

Logical Right Shift

1010 → 0101

(Division by 2 for unsigned numbers)

2. Arithmetic Shift

* Used for signed numbers

* Sign bit is preserved

Example:

Arithmetic Right Shift

1101 → 1110

3. Circular Shift (Rotate)

* Bits shifted out from one end enter at the other end

Example:

Rotate Left

1001 → 0011

Conclusion

Shift instructions are essential for fast arithmetic operations, data

compression, and bit manipulation.

1. (b) Define Control Memory. Explain

(5 Marks)

Definition
Control Memory is a special memory unit that stores microinstructions, which
control the execution of machine instructions in a microprogrammed control
unit.

Features of Control Memory

* Stores control words (microinstructions)

* Read-only or writable (ROM / RAM)

* Faster than main memory

* Accessed by control unit

Function

* Generates control signals for CPU operations

* Controls data transfer between registers

* Directs ALU operations

Conclusion

Control memory plays a crucial role in instruction execution and CPU control
in microprogrammed systems.

2. (a) Explain about Microinstruction Format in detail

(5 Marks)

Definition

Microinstruction format defines the structure of a microinstruction, specifying

how control signals and sequencing information are arranged.

Fields of a Microinstruction

1. Control Field
* Specifies micro-operations

* Controls registers, ALU, and memory

1. Condition Field

* Used for conditional branching

* Checks flags like Zero, Carry

1. Branch Field

* Specifies type of sequencing

* Example: Jump, Call, Return

1. Address Field

* Holds address of next microinstruction

Types

* Horizontal microinstruction (wide control word)

* Vertical microinstruction (encoded control signals)

Conclusion

Microinstruction format ensures efficient control signal generation and proper

sequencing of operations.

2. (b) What are RISC Instructions? Explain

(5 Marks)

Definition

RISC (Reduced Instruction Set Computer) instructions are simple and few in
number, designed for fast execution.

Characteristics

* Fixed instruction length

* Simple addressing modes

* Single-cycle execution

* Load–store architecture

Examples

* LOAD

* STORE

* ADD

* SUB

Advantages

* Faster execution

* Simple hardware design

* Efficient pipelining

Conclusion

RISC instructions improve performance and speed by simplifying instruction

execution.

3. (a) Define the following terms

(5 Marks)

i) Control Memory

Control memory is a special memory that stores microinstructions required

for generating control signals in a microprogrammed control unit.

ii) Address Sequencing

Address sequencing is the process of determining the address of the next
microinstruction to be executed.

Methods of Address Sequencing

* Incrementing microinstruction address

* Branching

* Conditional sequencing

Conclusion

Both control memory and address sequencing are essential for proper
microprogram execution.

3. (b) Explain about Microinstruction Format with neat sketch

(5 Marks)

Microinstruction Format

A microinstruction consists of multiple fields that specify control signals and

next instruction address.

Neat Sketch (to draw in exam)

| Control Field | Condition Field | Branch Field | Address Field |

Explanation

* Control Field: Generates control signals

* Condition Field: Tests status flags

* Branch Field: Decides next action

* Address Field: Stores next microinstruction address

Conclusion

A proper microinstruction format ensures systematic and efficient control of

CPU operations.

4. (a) Explain about various Addressing Modes

(5 Marks)

Definition

Addressing modes specify how the operand of an instruction is accessed.

Types of Addressing Modes

1. Immediate Addressing

* Operand is part of instruction

Example: ADD #5

1. Direct Addressing

* Address field contains operand address

1. Indirect Addressing

* Address field points to another address

1. Register Addressing

* Operand stored in register

1. Indexed Addressing

* Effective address = base + index

Conclusion

Addressing modes provide flexibility and efficient memory access.

4. (b) General Purpose Registers and Flag Registers

(5 Marks)

General Purpose Registers (GPR)

* Store data and intermediate results

* Used for arithmetic and logical operations

* Examples: R0, R1, R2

Flag Registers

* Store status information of ALU operations

Common Flags:

* Zero (Z)

* Carry (C)

* Sign (S)

* Overflow (V)

Importance

* GPR improves execution speed

* Flags help in decision making and branching

Conclusion

General purpose registers support data processing, while flag registers assist
in program control and conditional execution.

5. Explain in detail various types of Addressing Modes with examples

(10 Marks)

Introduction
Addressing modes define the method by which the operand of an instruction
is specified. They determine how the effective address of data is calculated.
Proper use of addressing modes improves program flexibility, execution
speed, and efficient memory usage.

1. Immediate Addressing Mode

* Operand is part of the instruction itself

* No memory access required for operand

Example:

ADD #5

(Adds the constant value 5)

Advantages: Fast execution

Disadvantage: Limited operand size

2. Direct Addressing Mode

* Address field contains the actual memory address of the operand

Example:

ADD 2000

(Operand is at memory location 2000)

Effective Address (EA):

EA = Address field

3. Indirect Addressing Mode

* Address field contains the address of another memory location that holds
the operand address
Example:

ADD @2000

Effective Address:

EA = M[Address]

Advantage: Greater address range

Disadvantage: Slower due to extra memory access

4. Register Addressing Mode

* Operand is stored in a CPU register

Example:

ADD R1

Advantages: Very fast, fewer memory accesses

Disadvantage: Limited number of registers

5. Register Indirect Addressing Mode

* Register contains the memory address of the operand

Example:

ADD @R1

Effective Address:

EA = (R1)

6. Indexed Addressing Mode

* Effective address is obtained by adding index register content to address
field

Example:

ADD 1000(R1)

Effective Address:

EA = Address + Index register

Used in: Array and table access

7. Relative Addressing Mode

* Effective address is obtained by adding displacement to Program Counter

Example:

BEQ LABEL

Effective Address:

EA = PC + Offset

Used in: Branch instructions

8. Stack Addressing Mode

* Operands are taken from the stack

* Uses Stack Pointer (SP)

Example:

PUSH A

POP A
Used in: Subroutines and expression evaluation

Conclusion

Addressing modes provide flexibility, efficient memory usage, and powerful

programming techniques. By supporting multiple addressing modes, a
processor can execute programs faster and more efficiently, making them a
vital component of computer architecture.

6. (a) Explain in detail about Data Transfer Instructions

(5 Marks)

Introduction

Data transfer instructions are used to move data between registers, memory,
and input/output devices. These instructions do not modify the data, they
only copy it from one location to another.

Common Data Transfer Instructions

1. LOAD (LDA / LD)

* Transfers data from memory to a register

Example:

LDA 2000

(Loads contents of memory location 2000 into accumulator)

2. STORE (STA / ST)

* Transfers data from a register to memory

Example:
STA 3000

3. MOVE (MOV)

* Transfers data between registers

Example:

MOV R1, R2

4. EXCHANGE (XCHG)

* Swaps contents of two registers

5. INPUT / OUTPUT Instructions

* Transfer data between CPU and I/O devices

Example:

IN PORT

OUT PORT

Features of Data Transfer Instructions

* No arithmetic or logical operation

* Fast execution

* Essential for program execution

Conclusion

Data transfer instructions form the foundation of instruction execution by

enabling smooth data movement between various system components.
6. (b) Discuss the Various Types of Instruction Formats

(5 Marks)

Introduction

Instruction format refers to the layout of bits in an instruction, specifying the

opcode and operand fields. Different formats are used to balance instruction
length, execution speed, and hardware complexity.

Types of Instruction Formats

1. Three-Address Instruction Format

* Contains opcode and three address fields

* Two operands and one result location

Example:

ADD R1, R2, R3

(R1 = R2 + R3)

Advantage: Fewer instructions

Disadvantage: Larger instruction size

2. Two-Address Instruction Format

* One operand acts as both source and destination

Example:

ADD R1, R2

(R1 = R1 + R2)

3. One-Address Instruction Format

* Uses accumulator implicitly

Example:

ADD X

(AC = AC + X)

4. Zero-Address Instruction Format

* Uses stack for operands

Example:

PUSH A

ADD

Conclusion

Different instruction formats provide trade-offs between code size and

execution efficiency, allowing processors to be designed for specific
performance goals.

7. What are the common fields found in instruction format? Explain various
instruction formats based on types of CPU Organization

(10 Marks)

Introduction

An instruction format defines the layout of bits in a machine instruction. It

specifies the operation to be performed and the operands involved. The
structure of instruction formats depends on the CPU organization, such as
accumulator-based, stack-based, or register-based systems.

Common Fields Found in an Instruction Format

1. Opcode Field

* Specifies the operation to be performed

* Examples: ADD, SUB, LOAD, STORE

2. Address / Operand Field

* Specifies the location of operand(s)

* Can refer to memory, register, or I/O location

3. Addressing Mode Field

* Specifies how the operand is accessed

* Examples: Immediate, Direct, Indirect, Register

4. Register Field

* Specifies the register(s) involved in the operation

* Used in register-based CPUs

5. Immediate / Constant Field

* Contains a constant value used directly in computation

Summary of Common Fields

Field Purpose

Opcode Operation

Address Operand location

Mode Access method

Register Register identification

Constant Immediate data

Instruction Formats Based on CPU Organization

1. Stack-Based CPU Organization (Zero-Address Instruction)

Description

* Operands are implicitly taken from the stack

* No address field required

Format

| Opcode |

Example

PUSH A

PUSH B

ADD

Advantages

* Short instruction length

* Simple hardware

Disadvantages

* More instructions needed

* Difficult random access

2. Accumulator-Based CPU Organization (One-Address Instruction)

Description

* One operand is in the accumulator

* Other operand is specified in the instruction

Format

| Opcode | Address |
Example

ADD X

(AC = AC + M[X])

Advantages

* Simple instruction format

* Less hardware complexity

Disadvantages

* Heavy dependence on accumulator

* More memory accesses

3. Register–Memory CPU Organization (Two-Address Instruction)

Description

* One operand is a register, the other is memory

* Result stored in one of them

Format

| Opcode | Register | Address |

Example

ADD R1, X

(R1 = R1 + M[X])

Advantages

* Fewer instructions

* Better performance than accumulator machines

4. Register–Register CPU Organization (Three-Address Instruction)

Description

* All operands are in registers

* Used in RISC processors

Format

| Opcode | Reg1 | Reg2 | Reg3 |

Example

ADD R1, R2, R3

(R1 = R2 + R3)

Advantages

* Very fast execution

* Efficient pipelining

Disadvantages

* Larger instruction size

* More registers required

Conclusion

Instruction formats define how operations and operands are encoded in

machine instructions. The CPU organization directly influences instruction
format design, balancing between simplicity, speed, and hardware
complexity. Proper instruction format selection improves overall system
performance

8. (a) Discuss the need of Memory Stack and Stack Limits

(5 Marks)

Memory Stack
A memory stack is a special area of memory used to store temporary data
such as return addresses, local variables, and intermediate results. It works
on the principle of LIFO (Last In First Out).

Need / Importance of Memory Stack

1. Subroutine Calls

* Stores return addresses during function or subroutine calls

* Ensures correct return to calling program

2. Temporary Storage

* Holds intermediate results during program execution

3. Interrupt Handling

* Saves program status and return address during interrupts

4. Expression Evaluation

* Used in stack-based instruction execution (PUSH, POP)

5. Efficient Memory Usage

* Dynamic allocation and deallocation of memory

Stack Limits

Definition

Stack limits define the maximum and minimum memory boundaries within
which the stack can grow.

* Upper Stack Limit – Prevents stack overflow

* Lower Stack Limit – Prevents stack underflow

Need for Stack Limits

* Protects memory from overflow/underflow errors

* Prevents overwriting of program data

* Ensures system stability and security

Conclusion

The memory stack is essential for program control and execution, while stack
limits ensure safe and error-free operation.

8. (b) Explain the General Register Organization of the Processor

(5 Marks)

Definition

General Register Organization refers to the arrangement of registers inside

the CPU and the mechanism used for data transfer and ALU operations.

Components of General Register Organization

1. General Purpose Registers (GPRs)

* Store data and intermediate results

* Used for arithmetic and logical operations

* Example: R0, R1, R2, R3

2. Common Bus System

* Allows data transfer between registers

* Implemented using multiplexers or tri-state buffers

3. Arithmetic Logic Unit (ALU)

* Performs arithmetic and logical operations

* Receives operands from registers

4. Control Unit
* Generates control signals

* Selects source and destination registers

* Controls ALU operations

Operation

* Two registers send data to ALU

* ALU processes data

* Result is stored back into a register

Conclusion

General register organization improves processing speed, reduces memory

access, and supports efficient CPU operation.

9. Explain the Microprogram Sequencer for a Control Memory with a Neat

Diagram

(10 Marks)

Introduction

A microprogram sequencer is a control unit component that determines the

address of the next microinstruction to be executed from control memory.

Control Memory

* Stores microinstructions

* Each microinstruction generates control signals

* Accessed using a Control Address Register (CAR)

Functions of a Microprogram Sequencer

1. Determines next microinstruction address

2. Supports sequential execution

3. Supports branching and conditional jumps

4. Handles interrupts

Main Components of Microprogram Sequencer

1. Control Address Register (CAR)

* Holds address of current microinstruction

2. Incrementer

* Increments CAR for next sequential instruction

3. Multiplexer

* Selects next address source

4. Branch Logic

* Decides branching based on condition flags

5. Control Memory

* Stores microinstructions

Neat Diagram (to draw in exam)

┌───────────────┐

│ Control │

│ Memory │

└──────┬────────┘

┌──────▼────────┐

│ Control │

│ Address Reg │

└──────┬────────┘
 │

┌────────▼─────────┐

│ Incrementer / │

│ Branch Logic │

└────────┬─────────┘

Next Address

Working

1. CAR fetches microinstruction from control memory

2. Control signals are generated

3. Sequencer decides next address

4. CAR is updated

5. Process continues until instruction completes

Conclusion

The microprogram sequencer ensures proper sequencing, branching, and

control of microinstructions, making it a key element of microprogrammed
control units.

UNIT - III

1. (a) Discuss about Complements in Data Representation

(5 Marks)

Introduction
Complements are used in data representation to simplify arithmetic
operations, especially subtraction, and to represent negative numbers in
digital computers.

Types of Complements

1. Radix Complement

For a number system with base r, the radix complement of a number N with
n digits is:

r^n−N

Examples

* 10’s complement (decimal)

10’s complement of 247 = 1000 − 247 = 753

* 2’s complement (binary)

2’s complement of 1010

→ 1’s complement = 0101

→ Add 1 = 0110

2. Diminished Radix Complement

It is given by:

(r^n−1)−N

Examples

* 9’s complement (decimal)

9’s complement of 247 = 999 − 247 = 752

* 1’s complement (binary)

1’s complement of 1010 = 0101

Importance of Complements
* Simplifies subtraction

* Represents negative numbers

* Reduces hardware complexity

Conclusion

Complements play a vital role in data representation and arithmetic

operations in digital computers.

1. (b) Explain Decimal Arithmetic Operations with Examples

(5 Marks)

Introduction

Decimal arithmetic operations are performed on decimal numbers (base-10).

The basic operations include addition, subtraction, multiplication, and
division.

1. Decimal Addition

Add digits column by column and carry if sum ≥ 10.

Example:

256

+ 189

-----

445

2. Decimal Subtraction

Subtract digits column by column, borrowing if required.

Example:
 542

− 268

-----

274

3. Decimal Multiplication

Multiply each digit and add partial products.

Example:

23 × 4 = 92

4. Decimal Division

Repeated subtraction or long division method.

Example:

144 ÷ 12 = 12

Conclusion

Decimal arithmetic operations are the foundation of numerical computation

and are widely used in everyday calculations and digital systems.

2. (a) Describe Fixed Point Representation in detail

(5 Marks)

Introduction

Fixed point representation is a method used to represent real numbers in

digital computers where the decimal (radix) point is fixed at a predetermined
position. It is commonly used for representing integers and fractional
numbers.

Concept of Fixed Point Representation

* The number has a fixed number of bits for the integer part and fractional
part

* The radix point position is assumed, not stored

* Can represent both signed and unsigned numbers

Types of Fixed Point Representation

1. Unsigned Fixed Point Representation

* All bits are used to represent magnitude

* Only positive numbers can be represented

Example:

Binary: 1011

Decimal: 11

2. Signed Fixed Point Representation

One bit is reserved for sign.

a) Sign-Magnitude

* MSB represents sign (0 = +, 1 = −)

Example:

+5 → 0101

−5 → 1101

b) 1’s Complement
* Negative number obtained by complementing all bits

Example:

+5 → 0101

−5 → 1010

c) 2’s Complement

* Negative number = 1’s complement + 1

* Most widely used representation

Example:

+5 → 0101

−5 → 1011

Advantages

* Simple hardware implementation

* Fast arithmetic operations

Disadvantages

* Limited range

* Precision loss for large fractional values

Conclusion

Fixed point representation is simple and efficient, making it suitable for

general-purpose computations, especially where high precision is not
required.

2. (b) Discuss Division Algorithms with examples

(5 Marks)

Introduction

Division algorithms are used in digital computers to perform division

operations using binary arithmetic. These algorithms are implemented using
shifts, subtraction, and comparisons.

Types of Division Algorithms

1. Restoring Division Algorithm

Working Principle

* Divisor is subtracted from partial remainder

* If result is negative, original value is restored

* Quotient bit is set accordingly

Steps

1. Shift partial remainder left

2. Subtract divisor

3. If result < 0 → restore and set quotient bit = 0

4. Else → keep result and set quotient bit = 1

Example

Divide 13 ÷ 3

13 ÷ 3 = 4 (Quotient), Remainder = 1

2. Non-Restoring Division Algorithm

Working Principle

* Avoids restoration step

* Adds or subtracts divisor based on previous remainder sign

Steps

1. Shift remainder

2. Add or subtract divisor

3. Set quotient bit based on sign of remainder

Advantage

* Faster than restoring division

* Fewer operations

Conclusion

Division algorithms enable computers to perform accurate binary division

efficiently. Among them, non-restoring division is preferred due to better
speed and reduced hardware complexity.

3. (a) Explain the flowchart for addition operation with sign-magnitude data

(5 Marks)

Introduction

In sign-magnitude representation, the most significant bit (MSB) represents

the sign

(0 = positive, 1 = negative) and the remaining bits represent the magnitude.

Addition of sign-magnitude numbers depends on the sign bits of the

operands.

Steps in Addition of Sign-Magnitude Numbers (Flowchart Explanation)

1. Start

* Read the two numbers A and B.

2. Separate Sign and Magnitude

* Extract sign bits SA and SB.

* Extract magnitudes MA and MB.

3. Compare Sign Bits

* If SA = SB (same sign):

* Add magnitudes:

M = MA + MB

* Result sign = SA

* If SA ≠ SB (different signs):

* Subtract smaller magnitude from larger magnitude:

M = |MA − MB|

* Result sign = sign of the larger magnitude.

4. Check Overflow

* If magnitude exceeds bit limit, overflow occurs.

5. Combine Sign and Magnitude

* Attach result sign to result magnitude.

6. Stop

Conclusion

Addition using sign-magnitude requires sign comparison, magnitude addition

or subtraction, and careful handling of overflow, making it more complex
than 2’s complement addition.

3. (b) Perform: Subtract 17 from 23 using Binary Code (Computer Method)

(5 Marks)

Given

23

17
23 - 17

23−17

Step 1: Convert Numbers to Binary

* 23

10

10111

23_{10} = 10111_2

2310 =101112

* 17

10

10001

17_{10} = 10001_2

1710 =100012
Step 2: Find 2’s Complement of 17

1. 1’s complement of 10001 → 01110

2. Add 1 → 01111

So, −17 = 01111 (2’s complement)

Step 3: Add to 23

10111 (23)

+ 01111 (−17)

--------

100110

Step 4: Discard Carry

Result = 00110

Step 5: Convert Result to Decimal

00110₂ = 6₁₀

Final Answer

23

17

23 - 17 = \boxed{6}
23−17=6

Conclusion

Binary subtraction in computers is performed using 2’s complement addition,

which simplifies hardware design and avoids direct subtraction circuits.

4. (a) Explain Booth’s Algorithm for Signed Multiplication

(5 Marks)

Introduction

Booth’s algorithm is an efficient method for multiplying signed binary

numbers represented in 2’s complement form. It reduces the number of
addition and subtraction operations and is widely used in computer
arithmetic.

Registers Used

* A – Accumulator

* Q – Multiplier

* M – Multiplicand

* Q-1 – Extra bit (initially 0)

Booth’s Algorithm Rules

Examine the last bit of Q (Q0) and Q-1:

Q0 Q-1 Operation

0 0 No operation

0 1 A←A+M

1 0 A←A−M

1 1 No operation
Steps of Booth’s Algorithm

1. Initialize A = 0, Q = multiplier, M = multiplicand, Q-1 = 0

2. Check (Q0, Q-1) and perform operation as per table

3. Perform arithmetic right shift on (A, Q, Q-1)

4. Decrement count

5. Repeat until count = 0

Advantages

* Handles both positive and negative numbers

* Fewer arithmetic operations

* Efficient hardware implementation

Conclusion

Booth’s algorithm provides an efficient and systematic method for signed

binary multiplication, improving speed and reducing complexity.

4. (b) Draw the Flowchart for Floating Point Division

(5 Marks)

Floating Point Division

Floating point division involves dividing two numbers represented in the

form:

Number = Sign × Mantissa × Base^Exponent

Steps in Floating Point Division (Flowchart Explanation)

1. Start
2. Separate Sign, Exponent, Mantissa

* Sign of result = Sign₁ ⊕ Sign₂

3. Subtract Exponents

* Exponent = Exponent₁ − Exponent₂

4. Divide Mantissas

* Mantissa = Mantissa₁ ÷ Mantissa₂

5. Normalize Result

* Adjust mantissa and exponent

6. Check for Overflow / Underflow

7. Round the Result

8. Stop

How to Draw the Flowchart in Exam

Start

Separate Sign, Exponent, Mantissa

Exponent = E1 − E2

Mantissa = M1 ÷ M2

Normalize Result

Check Overflow / Underflow

Stop
Conclusion

Floating point division is performed by dividing mantissas and subtracting

exponents, followed by normalization to maintain standard form.

5. (a) Explain Floating Point Representation of Decimal Numbers

(5 Marks)

Introduction

Floating point representation is used to represent very large and very small
decimal numbers in computers. In this method, numbers are represented in
scientific notation, allowing a wide range of values with limited bits.

General Form

A floating point number is represented as:

Number=(−1)^Sign × Mantissa × Base^Exponent

Components of Floating Point Representation

1. Sign Bit

* Determines whether the number is positive or negative

* 0 → Positive, 1 → Negative

2. Mantissa (Significand)

* Represents the significant digits of the number

* Usually normalized (first digit non-zero)

3. Exponent

* Indicates the position of the decimal point

* Stored with a bias to allow positive and negative values

Example
Decimal number: +123.45

Scientific notation:

123.45 = 1.2345 × 10^2

* Sign = 0

* Mantissa = 1.2345

* Exponent = 2

Advantages

* Can represent very large and very small numbers

* High precision compared to fixed-point

Disadvantages

* Complex hardware

* Rounding errors may occur

Conclusion

Floating point representation is essential for scientific and real-time

applications where a wide range of decimal values must be handled
efficiently.

5. (b) Explain the Decimal Addition Operation with a Neat Diagram

(5 Marks)

Introduction

Decimal addition is the process of adding two decimal numbers digit by digit,
considering carry propagation when the sum exceeds 9. Computers perform
this operation using binary-coded decimal (BCD) internally.
Steps in Decimal Addition

1. Align the Decimal Points

2. Add Digits Column by Column

3. Generate Carry if Sum ≥ 10

4. Add Carry to Next Higher Digit

5. Repeat Until All Digits Are Added

Example

Add: 278 + 459

278

+ 459

-----

737

Neat Diagram (Decimal Addition Process)

Digit A ──┐

├──► Decimal Adder ───► Sum

Digit B ──┘ │

└──► Carry to next digit

Explanation of Diagram

* Each digit of the numbers is applied to the decimal adder

* The adder produces a sum digit and a carry

* Carry is forwarded to the next higher digit

Conclusion

Decimal addition is a fundamental arithmetic operation. Proper handling of

carry propagation ensures accurate results in digital systems.

6. (a) Explain the Subtraction Operation with Signed 2’s Complement Data

(5 Marks)

Introduction

In digital computers, subtraction is performed using 2’s complement

arithmetic. Instead of using a separate subtraction circuit, the computer adds
the 2’s complement of the subtrahend to the minuend, making hardware
design simpler and faster.

Steps in 2’s Complement Subtraction

To compute:

A-B

1. Represent both numbers in binary

2. Find the 2’s complement of B

* Take 1’s complement of B

* Add 1 to the result

3. Add the 2’s complement of B to A

4. Discard the carry (if any)

5. If no carry occurs, the result is negative and already in 2’s complement

form

Advantages

* No separate subtraction hardware needed

* Easy handling of negative numbers

* Fast and efficient operation

Conclusion

2’s complement subtraction simplifies arithmetic operations and is the most

widely used method in digital computers.

6. (b) Explain in Brief Fixed Point Data Representation

(5 Marks)

Introduction

Fixed point data representation is a method in which the decimal (radix)

point position is fixed. It is mainly used to represent integers and fractional
numbers in digital systems.

Concept

* A fixed number of bits are allocated for:

* Integer part

* Fractional part

* Radix point is assumed, not stored

Types of Fixed Point Representation

1. Unsigned Fixed Point

* Represents only positive numbers

Example:

1011₂ = 11₁₀
1. Signed Fixed Point

Uses one bit for sign.

a) Sign-Magnitude

* MSB = sign bit

b) 1’s Complement

* Negative obtained by bitwise complement

c) 2’s Complement

* Negative = 1’s complement + 1

* Most commonly used

Advantages

* Simple and fast arithmetic

* Easy hardware implementation

Disadvantages

* Limited range

* Precision loss for large fractional values

Conclusion

Fixed point representation is efficient and simple, making it suitable for

general-purpose arithmetic operations where high precision is not required.

UNIT - IV

1. (a) Explain Hardware Organization and Match Logic of Associative Memory

(5 Marks)
Associative Memory (CAM)

Associative Memory, also called Content Addressable Memory (CAM),

retrieves data based on content rather than address. It is mainly used in
cache memory and virtual memory systems.

Hardware Organization of Associative Memory

The basic hardware consists of:

1. Memory Array

* Stores data words

* Each word has multiple bits

2. Argument Register (AR)

* Holds the search key (content to be matched)

3. Key Register (KR) / Mask Register

* Specifies which bits should participate in comparison

4. Match Logic

* Compares AR with all memory words in parallel

5. Match Register

* Indicates which memory word(s) matched

Match Logic

* Each bit of AR is compared with corresponding bit of memory word

* If all selected bits match → Match = 1

* Comparison is done simultaneously for all words

Operation:

* Parallel comparison

* Fast search operation

* Output gives the address of matching word

Conclusion

Associative memory uses parallel hardware and match logic to provide very
fast searching, making it ideal for cache and TLB applications.

1. (b) What are Various Modes of Transfer? Explain

(5 Marks)

Modes of Data Transfer

Data transfer modes define how data is transferred between CPU, memory,
and I/O devices.

1. Programmed I/O

* CPU controls data transfer

* CPU continuously checks device status

Advantages: Simple

Disadvantages: CPU time wasted

2. Interrupt-Driven I/O

* I/O device sends interrupt when ready

* CPU executes ISR

Advantages: Better CPU utilization

Disadvantages: Interrupt overhead

3. Direct Memory Access (DMA)

* DMA controller transfers data directly between memory and I/O

* CPU involvement is minimal

Advantages: High speed

Disadvantages: Complex hardware

Conclusion

Different transfer modes balance speed, CPU involvement, and hardware

complexity based on system requirements.

2. Discuss about Direct Mapping and Set Associative Mapping

(10 Marks)

Introduction

Cache mapping techniques define how main memory blocks are placed into
cache lines. The two important techniques are Direct Mapping and Set
Associative Mapping.

Direct Mapping

Concept

* Each memory block maps to exactly one cache line

Mapping Formula

Cache line

Main memory block number

mod

(
Number of cache lines

\text{Cache line} = (\text{Main memory block number}) \bmod (\

text{Number of cache lines})

Cache line=(Main memory block number)mod(Number of cache lines)

Address Format

| Tag | Line | Word |

Advantages

* Simple hardware

* Fast access

* Low cost

Disadvantages

* High conflict misses

* Poor cache utilization

Set Associative Mapping

Concept

* Cache is divided into sets

* Each memory block maps to any line within a specific set

Address Format

| Tag | Set | Word |

Advantages

* Reduced conflict misses

* Better performance than direct mapping

Disadvantages

* More complex hardware

* Slightly slower than direct mapping

Comparison Table

Feature Direct Mapping Set Associative Mapping

Mapping One-to-one One-to-set

Hardware Simple Moderate

Miss rate High Lower

Speed Very fast Slightly slower

Conclusion

Direct mapping is simple and fast, while set associative mapping offers
better cache performance by reducing conflicts. The choice depends on cost,
complexity, and performance requirements.

3. (a) Explain the Block Diagram of I/O Interface

(5 Marks)

Introduction

An I/O interface acts as a communication link between the CPU and

peripheral devices. It resolves differences in speed, data format, and control
signals between CPU and I/O devices.

Main Components of I/O Interface

1. Data Register
* Temporarily holds data being transferred

* Transfers data between CPU and I/O device

1. Status Register

* Indicates device status (ready, busy, error)

* Helps CPU decide when to perform I/O operation

1. Control Register

* Stores control commands from CPU

* Initiates read/write operations

1. Address Decoder

* Selects the required I/O device

* Activates interface when its address matches

1. Control Logic

* Generates timing and control signals

* Coordinates data transfer

Working

* CPU sends address and control signal

* Address decoder selects device

* Data transferred via data register

* Status register updates device state

Conclusion

The I/O interface ensures smooth and reliable communication between CPU
and peripheral devices.

3. (b) Write a Short Note on Cache Memory

(5 Marks)

Definition

Cache memory is a small, high-speed memory located between the CPU and
main memory. It stores frequently accessed data and instructions to improve
system performance.

Characteristics of Cache Memory

* Faster than RAM

* Smaller in size

* Costly compared to main memory

* Built using SRAM

Working Principle

* Uses locality of reference

* Temporal locality

* Spatial locality

* On cache hit → data served from cache

* On cache miss → data fetched from main memory

Types of Cache

* L1 Cache (fastest, smallest)

* L2 Cache

* L3 Cache (shared cache)

Conclusion

Cache memory significantly reduces memory access time and improves

overall CPU performance.
4. Compare Cache Memory and Main Memory

(10 Marks)

Introduction

Cache memory and main memory differ in speed, size, cost, and
functionality. Both are essential for efficient computer operation.

Comparison Table

Feature Cache Memory Main Memory

Speed Very fast Slower than cache

Size Small Large

Cost Very expensive Less expensive

Technology SRAM DRAM

Access Time Few nanoseconds Higher access time

Location Between CPU and RAM Directly connected to CPU

Purpose Stores frequently used data Stores programs and data

Power Consumption Low Higher

Data Availability Limited Large storage

Example L1, L2, L3 Cache RAM

Advantages Comparison

* Cache → Faster execution, reduced CPU wait time

* Main Memory → Large storage capacity, holds entire programs

Conclusion

Cache memory enhances speed, while main memory provides capacity.

Together, they form an efficient memory hierarchy for high system
performance.
5. (a) Draw the Block Diagram of a Typical DMA Controller and Explain

(5 Marks)

Direct Memory Access (DMA) Controller

A DMA controller allows high-speed data transfer between I/O devices and
main memory without continuous CPU involvement.

Block Diagram of DMA Controller

(Draw this neatly in exam)

┌──────────────┐

│ DMA Control │

│ Logic │

└──────┬───────┘

┌─────────────▼─────────────┐

│ Address Register │

└─────────────┬─────────────┘

┌─────────────▼─────────────┐

│ Count Register │

└─────────────┬─────────────┘

┌─────────────▼─────────────┐

│ Data Register │

└─────────────┬─────────────┘

│
 Main Memory ↔ I/O Device

Main Components and Functions

1. Address Register

* Holds the memory address for data transfer

* Automatically incremented after each transfer

1. Count Register

* Stores number of bytes/words to be transferred

* Decremented after every transfer

1. Data Register

* Temporarily holds data during transfer

1. Control Logic

* Generates read/write signals

* Requests and releases CPU control

Working

* CPU initializes DMA controller

* DMA takes control of system bus

* Transfers data directly between memory and I/O

* Interrupts CPU after completion

Conclusion

DMA controller improves system performance by reducing CPU overhead

during large data transfers.

5. (b) Explain Daisy-Chain Priority Interrupt in Detail

(5 Marks)

Definition

Daisy-chain priority interrupt is a hardware priority scheme in which multiple

devices are connected serially to determine interrupt priority.

Working Principle

CPU → Device 1 → Device 2 → Device 3 → ...

1. All devices share a common interrupt request line

2. CPU sends an interrupt acknowledge signal (INTA)

3. INTA passes through devices in sequence

4. First requesting device captures the signal

5. Lower-priority devices are blocked

Priority Order

* Device closest to CPU → Highest priority

* Device farthest from CPU → Lowest priority

Advantages

* Simple hardware implementation

* Easy to understand

Disadvantages

* Fixed priority (can cause starvation)

* Propagation delay

Conclusion
Daisy-chain interrupt provides a simple priority mechanism, suitable for small
systems.

6. (a) Address Format of Main Memory (Cache Mapping Problem)

(5 Marks)

Given

* Cache: 2-way set associative

* Line size = 16 bytes

* Cache size = 8 KB

* Main memory = 64 MB

* Memory is byte addressable

Step-1: Main Memory Address Size

64 MB=2^26⇒Address size = 26 bits

Step-2: Offset Bits

16 bytes=2^4⇒Offset = 4 bits

Offset = 4 bits

Step-3: Number of Sets

Number of sets= 8K /16 x 2 = 8192 / 32 = 256 = 2^8

Index (Set) bits=8

Step-4: Tag Bits

Tag=26−(8+4)=14 bits

Main Memory Address Format

| Tag (14 bits) | Set Index (8 bits) | Offset (4 bits) |

Conclusion

The address is divided into Tag, Set index, and Offset to support 2-way set
associative cache mapping.

6. (b) How Does SDRAM Differ from Ordinary DRAM?

(5 Marks)

Definition

SDRAM (Synchronous DRAM) operates in synchronization with the system

clock, while ordinary DRAM is asynchronous.

Differences Between SDRAM and DRAM

Feature DRAMSDRAM

Clock Asynchronous Synchronous

Speed Slower Faster

Data Transfer One operation at a timePipelined operations

Performance LowerHigher

CPU Sync No Yes

Cost Cheaper Costlier

Advantages of SDRAM

* Higher data transfer rate

* Better performance

* Suitable for modern processors

Conclusion

SDRAM provides faster and more efficient memory access compared to

ordinary DRAM due to clock synchronization.

7. (a) Explain the Major Differences between the Central Computer and
Peripherals. How to Resolve these Differences?

(5 Marks)

Introduction

The central computer (CPU) and peripheral devices differ greatly in their
operation, speed, and data handling. These differences must be resolved to
ensure smooth and reliable data transfer.

Major Differences

1. Speed

* CPU operates at very high speed

* Peripherals are much slower

1. Data Format

* CPU processes data in binary form

* Peripherals may use character, analog, or serial formats

1. Data Transfer Rate

* CPU transfers data in parallel

* Peripherals usually transfer data serially

1. Control Mechanism

* CPU follows strict timing and control signals

* Peripherals operate independently

1. Electrical and Physical Characteristics

* Different voltage levels and signal timings

Methods to Resolve These Differences

1. I/O Interface

* Acts as a bridge between CPU and peripherals

* Handles data conversion and control signals

1. Buffer Registers

* Temporarily store data to match speed differences

1. Interrupts

* Allow peripherals to signal CPU when ready

1. DMA (Direct Memory Access)

* Transfers data directly between memory and I/O devices

1. Handshaking Mechanisms

* Ensure proper timing and synchronization

Conclusion

The differences between CPU and peripherals are resolved using interfaces,
buffers, interrupts, and DMA, enabling efficient I/O operations.

7. (b) Discuss the Strobe Control Method of Asynchronous Data Transfer

(5 Marks)

Asynchronous Data Transfer

Asynchronous data transfer occurs without a common clock between sender

and receiver. Synchronization is achieved using control signals.
Strobe Control Method

In the strobe method, a single control signal (strobe) is used to indicate when
data is valid.

Types of Strobe Control

1. Source-Initiated Strobe

* Source places data on the bus

* Source activates strobe to indicate valid data

* Destination reads data when strobe is active

Limitation: Destination readiness not confirmed

2. Destination-Initiated Strobe

* Destination activates strobe to request data

* Source places data on the bus in response

Limitation: Source readiness not confirmed

Advantages

* Simple control mechanism

* Requires fewer control lines

Disadvantages

* No confirmation of data receipt

* Timing issues may occur

Conclusion

The strobe control method is simple but less reliable. It is suitable for low-
speed asynchronous data transfer, while handshaking provides better
reliability.
UNIT - V

1. (a) Interprocessor Arbitration

(5 Marks)

Definition

Interprocessor arbitration is the mechanism used to decide which processor

gets control of a shared resource (such as memory, bus, or I/O) in a
multiprocessor system.

Need for Interprocessor Arbitration

* Multiple processors may request the same shared resource

* Prevents conflicts and data corruption

* Ensures fair and orderly access

Arbitration Methods

1. Centralized Arbitration

* A single arbiter controls access

* Simple but may become a bottleneck

1. Distributed Arbitration

* Each processor participates in arbitration

* Faster and more reliable

1. Fixed Priority Arbitration

* Each processor has a fixed priority

* Higher-priority processor always wins

1. Dynamic Priority Arbitration

* Priority changes over time

* Prevents starvation

Conclusion

Interprocessor arbitration ensures efficient and conflict-free resource sharing

in multiprocessor systems.

1. (b) Four-Segment Instruction Pipeline

(5 Marks)

Definition

An instruction pipeline increases CPU performance by overlapping the

execution of multiple instructions, dividing instruction processing into stages.

Four Segments of Instruction Pipeline

1. Instruction Fetch (IF)

* Fetches instruction from memory

1. Instruction Decode (ID)

* Decodes opcode and operands

1. Execute (EX)

* Performs arithmetic or logical operation

1. Write Back (WB)

* Stores result in register or memory

Operation

* While one instruction is executing, others are being fetched and decoded

* Improves throughput
Advantages

* Increased CPU utilization

* Faster instruction execution

Conclusion

A four-segment pipeline improves system performance by parallel instruction

processing.

2. Explain the following

2. (a) Interprocess Communication and Synchronization

(5 Marks)

Interprocess Communication (IPC)

Definition

IPC allows processes to exchange data and information in a multiprocessor or

multitasking environment.

Methods of IPC

1. Shared Memory

* Processes share a common memory area

1. Message Passing

* Data exchanged using send/receive messages

Process Synchronization

Definition

Synchronization ensures orderly execution of processes and avoids race

conditions.
Synchronization Techniques

* Semaphores

* Mutex locks

* Monitors

Conclusion

IPC and synchronization are essential for correct and coordinated execution
of concurrent processes.

2. (b) Array Processors

(5 Marks)

Definition

An array processor is a parallel processing system consisting of multiple

processing elements (PEs) that execute the same instruction on different
data simultaneously.

Characteristics

* SIMD (Single Instruction, Multiple Data) architecture

* High computational speed

* Used for vector and matrix operations

Applications

* Image processing

* Scientific simulations

* Weather forecasting
Advantages

* High performance

* Efficient for repetitive computations

Conclusion

Array processors provide massive parallelism, making them ideal for data-
intensive applications.

3. (a) Explain about Instruction Pipelining with an Example

(5 Marks)

Definition

Instruction pipelining is a technique used to increase CPU throughput by

overlapping the execution of multiple instructions. The instruction execution
is divided into stages, and each stage processes a different instruction
simultaneously.

Pipeline Stages (Typical)

1. IF – Instruction Fetch

2. ID – Instruction Decode

3. EX – Execute

4. WB – Write Back

Example

Consider three instructions: I1, I2, I3

Clock Cycle Stage 1 Stage 2 Stage 3 Stage 4

C1 I1–IF

C2 I2–IF I1–ID
C3 I3–IF I2–ID I1–EX

C4 I3–ID I2–EX I1–WB

C5 I3–EX I2–WB

C6 I3–WB

Advantages

* Increased instruction throughput

* Better CPU utilization

Limitation

* Pipeline hazards (data, control, structural)

Conclusion

Instruction pipelining improves performance by parallel execution of

instruction stages, reducing overall execution time.

3. (b) Discuss about the Serial Arbitration Technique

(5 Marks)

Definition

Serial arbitration is a bus arbitration technique used to decide which device

gets control of a shared bus. Devices are connected in a serial (daisy-chain)
manner.

Working

* All devices share a common bus request line

* CPU sends a bus grant signal

* Grant signal passes serially from one device to the next

* The first requesting device captures the bus

* Remaining devices are blocked

Priority Scheme

* Device closest to CPU → Highest priority

* Device farthest from CPU → Lowest priority

Advantages

* Simple hardware

* Low cost

Disadvantages

* Fixed priority → starvation possible

* Propagation delay

Conclusion

Serial arbitration is simple and economical, suitable for small systems with
limited devices.

4. (a) Explain in brief Inter-Processor Communication

(5 Marks)

Definition

Inter-processor communication (IPC) refers to the methods used by multiple

processors to exchange data and coordinate execution in a multiprocessor
system.

Methods of Inter-Processor Communication

1. Shared Memory

* Processors communicate via a common memory area

* Requires synchronization mechanisms

1. Message Passing

* Data exchanged through send/receive messages

* Suitable for loosely coupled systems

Synchronization

* Semaphores, locks, and barriers are used

* Prevent race conditions and ensure consistency

Conclusion

Inter-processor communication enables cooperation and coordination among

processors for efficient parallel processing.

4. (b) Discuss the Characteristics of Multiprocessors

(5 Marks)

Multiprocessor System

A multiprocessor system consists of two or more processors that share

memory, I/O, and system resources.

Key Characteristics

1. Parallel Processing

* Multiple processors execute tasks simultaneously

1. Shared Memory

* Common address space for all processors

1. High Throughput

* Increased performance and faster execution

1. Reliability
* Failure of one processor does not halt the system

1. Scalability

* Processors can be added to improve performance

Conclusion

Multiprocessors provide high performance, reliability, and scalability, making

them ideal for scientific and real-time applications.

5. (a) What is Parallel Processing? Explain Flynn’s Classification of Computers

(5 Marks)

Parallel Processing

Parallel processing is the technique of performing multiple computations

simultaneously by using more than one processing unit. It improves
execution speed, throughput, and system performance.

Flynn’s Classification

Flynn classified computer architectures based on the number of instruction

streams and data streams.

1. SISD – Single Instruction Single Data

* One instruction operates on one data item

* Conventional uniprocessor systems

Example: Single-core CPU

2. SIMD – Single Instruction Multiple Data

* Same instruction executed on multiple data items

* Used in vector and array processors

Example: Vector processors, GPUs

3. MISD – Multiple Instruction Single Data

* Different instructions operate on the same data

* Rare in practice

Example: Fault-tolerant systems

4. MIMD – Multiple Instruction Multiple Data

* Multiple processors execute different instructions on different data

* Most common multiprocessor architecture

Example: Multicore processors

Conclusion

Parallel processing improves performance, and Flynn’s classification provides

a systematic way to categorize parallel computer architectures.

5. (b) Illustrate Vector Operations and Vector Processing

(5 Marks)

Vector Processing

Vector processing performs operations on entire vectors (arrays of data)

instead of individual elements, enabling high-speed computation.

Vector Operations

1. Vector Addition

C[i]=A[i]+B[i]

2. Vector Subtraction
C[i]=A[i]−B[i]

3. Vector Multiplication

C[i]=A[i]×B[i]

4. Scalar-Vector Operation

C[i]=k×A[i]

Vector Processing

* Uses vector registers to store multiple data elements

* Executes one instruction on all elements in parallel

* Reduces instruction fetch and decode overhead

Applications

* Scientific computing

* Image processing

* Matrix and array operations

Conclusion

Vector processing provides high performance for data-parallel tasks by

efficiently executing vector operations.

6. (a) Discuss about RISC Pipeline

(5 Marks)

RISC Pipeline
RISC (Reduced Instruction Set Computer) architecture uses simple and fixed-
length instructions, making it ideal for efficient pipelining.

Pipeline Stages in RISC

1. IF – Instruction Fetch

2. ID – Instruction Decode & Register Fetch

3. EX – Execute / Address Calculation

4. MEM – Memory Access

5. WB – Write Back

Features

* One instruction per cycle

* Load-store architecture

* Simple addressing modes

Advantages

* High throughput

* Easy hazard handling

* Efficient hardware utilization

Conclusion

RISC pipelines achieve high performance through simple instructions and

efficient pipeline design.

6. (b) What is Cache Coherence Problem? Discuss Solutions

(5 Marks)
Cache Coherence Problem

Cache coherence problem occurs in multiprocessor systems when multiple

caches hold copies of the same memory location, leading to inconsistent
data.

Causes

* One processor updates memory

* Other caches still hold old data

Solutions to Cache Coherence

1. Snooping Protocols

* Caches monitor the bus for memory updates

* Common protocols: MSI, MESI

2. Directory-Based Protocols

* Central directory tracks cache blocks

* Used in large multiprocessor systems

3. Write-Invalidate Protocol

* Invalidates other cache copies on write

4. Write-Update Protocol

* Updates all cache copies immediately

Conclusion

Cache coherence solutions ensure data consistency across caches, which is

crucial for correct execution in multiprocessor systems.